Typical consumer communication products seek to minimize the number of reference frequencies used within to minimize total bill of materials and product construction cost. Common frequency synthesis solutions rely on a dual modulus prescaler capable of dividing a radio frequency clock signal by a configurable divisor, being either N or N+1, where N is an integer. Such a dual modulus prescaler allows many frequencies to be generated while requiring a single crystal oscillator for an input clock having a reference frequency. Conventional dual modulus prescalers demands that the reference frequency be equal to the smallest step between two adjacent frequencies of the synthesized frequencies.
The conventional prescalers are commonly implemented through the application of two distinct classes of circuit, toggle flip-flops and finite state machines. Repeated use of a toggle flip-flop inherently halves the frequency of the input clock signal, providing a division factor of 2. Repeated use allows division by a modulus of the form 2N.
Dual modulus action is often provided via a fully synchronous circuit built through the repeated use of D-type flip-flops to form a finite state machine. The finite state machine has states that are configured to follow a repeated pattern in response to the input clock. The repeated pattern creates a lower output frequency than the reference frequency of the input clock.
A modulus control signal is commonly used to select one of several repeated patterns permitting the input clock to be divided by one of two or more moduli. Therefore, the finite state machine approach provides multiple modulus prescalers capable of dividing by multiple moduli which differ by an integer (usually unity). Coupling the two distinct classes of circuits allows higher value moduli to be realized. When applied within a frequency synthesizer, the multiple modulus prescalers generate a synthesized clock with a frequency that is an integer fraction of the reference frequency.
Implementation of a dual modulus prescaler capable of division by either N or N+0.5 allows the frequency reference to be twice the smallest frequency step within the system. Division by N+0.5 provides well known and documented performance benefits to the consumer product. Division by either N or N-0.5 provides equivalent operational and performance benefits.
Implementation of a dual modulus prescaler capable of division by the factor N+0.5 demands a circuit capable of dividing an input clock signal by a multiple of 0.5. Furthermore, such a circuit must be capable of operation at RF frequencies for the dual modulus prescaler to be of practical use in a communications application. Generation of dual moduli differing by a factor of 0.5 also precludes the use of completely synchronous logic techniques based exclusively around either the rising or falling edges of a synchronization signal for circuit development.
A first conventional approach uses two identical division circuits, each clocked from opposite edges of the input clock (i.e., one from the rising edge, one from the falling edge) to divide the input clock by a predetermined factor. The two division circuits present two output signals that are identical to each other but time shifted with respect to each other. One of the two output signals is selected as an output waveform during any given period. Choice of an appropriate time to switch the selection between the output signals allows the output waveform to be time shifted, providing division by a factor of the form N+0.5, where N is an integer.
Several factors limit the applicability of the first conventional approach. Since two instances of the same division circuit are used (each capable of dividing by a factor N, where N is an integer, and each clocked from opposite phases of the input clock), the total die area and power consumption is roughly double that of a division circuit capable of dividing only by a factor N. Some commonality usually exists between the two instances of the division circuit hence minor area and/or power optimization is possible.
Another limitation of the first conventional approach is that memory elements, usually flip-flops, in the two division circuits are in some unknown state upon application of power. The two instances of the division circuit should operate in a locked fashion but will not necessarily be locked in the appropriate way when power is initially applied. Some mechanism for resetting the memory elements is required. For logic capable of operation at a maximum speed permissible by a given geometry manufacturing process, incorporation of any reset mechanism degrades operation by a significant margin. To provide operation of a memory element with some reset mechanism that is equivalent to that of a memory element without reset demands increased die area (corresponding to product cost) and increased power (impacting both product cost, product characteristics, die packaging and other circuits on the IC).
A second conventional approach controls an inversion of the input clock prior to a division circuit allowing the phase of the input clock to be advanced or retarded. Selection of times when the inversion of the input clock takes place provides division by a factor of the form N+0.5, where N is an integer.
Several factors also limit the applicability of the second conventional approach. Controlled inversion of a local oscillator signal, such as an output of a voltage controlled oscillator and/or a current controlled oscillator, can be performed in several ways. Inversion circuit examples may include exclusive-OR gates or a multiplexor. However, the decision when to invert the input clock takes place synchronous to the input clock. Consequently, there must always be a latency between the circuit determining when to invert the input clock and the circuit implementing the inversion itself. The latency manifests itself as a glitch on the resultant signal. It is well documented that signal glitches taking place on the input clock or a synchronization signal can cause operational failure and reliability issues.